1) Field of the Invention
The present invention relates to a semiconductor device and a method for testing the semiconductor device. More specifically, the present invention relates to testing a semiconductor memory device in a DQ-compression test mode.
2) Description of the Related Art
Semiconductor memory devices such as DRAM (dynamic random access memory) typically have 16 or more pads that are used to input and output data. When testing semiconductor memory devices, probe pins of testing devices are brought into contact with such input/output pads. However, as many semiconductor memory devices are usually tested simultaneously, there are not enough probe pins to contact all of the pads. Therefore, a testing method in a DQ compression test (also referred to as I/O compression test or I/O contraction test) mode is employed, so that only about four pads need to contact a probe pin, respectively.
In the DQ-compression testing method, a predetermined test pattern is installed as a DQ-compression test mode code. When the test mode code is input, data is written not only in cells connected to input/output pads that contact the probe pins, but also in cells connected to input/output pads that do not contact the probe pins. Thus, interference between bit lines connected to cells and conditions between storage (capacitor) of cells can be tested.
FIG. 9 is a sequence of a testing method in a conventional DQ-compression test mode. Test mode entry 11 is executed to input test pattern-0 (TP0), and data for test pattern-0 (TP0) is written 12 and read 13. Subsequently, test mode entry 14 is executed to input test pattern-1 (TP1), and data for test pattern-1 (TP1) is written 15 and read 16. Although not shown, the same sequence is repeated for test pattern-2 (TP2) onwards.
There are various configurations of semiconductor memory devices to execute tests in the DQ-compression test mode. For example, there is known a semiconductor memory device that includes a selecting unit that selects input terminals for inputting test patterns and a generating unit that generates physical patterns (refer to Japanese Patent Application Laid-Open Publication No. 2000-182398). The selecting unit selects a plurality of line groups from at least either bit lines or word lines. Then, the selecting unit selects whether to input a predetermined test pattern to be used in a specific test for the semiconductor memory device, in the terminal of each selected line group. The generating unit inputs predetermined data in the selected line groups to input the test pattern, outputs predetermined data to data buses connected to the selected line groups, and also outputs predetermined data to data buses of line groups other than the selected line groups.
Another example of such semiconductor memory device includes an I/O compressing unit. The I/O compressing unit writes column address data of an external address of the write operation, as an I/O compression test pattern, in a memory cell of a preselected bank. The I/O compression test pattern simultaneously measures a plurality of multi-bit synchronous DRAMs in the test mode. The I/O compressing unit retains column address data of an external address of the read operation as comparative data, in a retaining unit other than the memory cell. The I/O compressing unit then reads the data from the memory cell and compares it with the comparative data, and outputs the comparison results outside as 1 bit signals (refer to Japanese Patent Application Laid-Open Publication No. 2003-7097). Yet another example of such semiconductor memory device includes an I/O contraction test function capable of writing independent, arbitrary data into a plurality of memory cells selected by one word line and one column selection line. The I/O contraction test function writes independent data into adjacent memory cells. The memory cell into which data is written is different to the memory cell from which data is read (refer to Japanese Patent Application Laid-Open Publication No. 2000-40397).
However, in the conventional DQ-compression test mode, every time a test pattern for bit lines is changed, a test mode entry needs to be executed to input the test code, which leads to increased time and cost.